What Computer Chips Will Look Like in 2045

Every modern chip begins as a disc of silicon and ends as a lattice of switches small enough that thousands could hide inside a red blood cell. Right now, the industry that makes those switches cannot keep up with itself. This conversation with Intel's process and packaging leaders opens with Pushkar Ronde noting that AI has pushed computing demand to "easily forty to fifty percent above" Intel's maximum capacity (00:00), a shock, he says, with no precedent in the history of chipmaking.

Chris Auth, who runs development of Intel's manufacturing processes, is in the middle of building the next one, called 14A, due out in roughly two to three years. The process has already been in development for three-plus years, and getting it into factories involves roughly 2,000 individual manufacturing steps that each need fine-tuning before the line can run thousands of wafers a week (01:35). Auth's team learned how costly ambition can be from Intel's ten-nanometer node: targeted for 2016, it did not reach manufacturing until 2018 (03:12). The chief culprit was extreme ultraviolet lithography, or EUV, a technique that prints chip patterns using light with a wavelength of just 13.5 nanometers, about fourteen times shorter than the light it replaced (05:13). Intel judged EUV unready in the mid-2010s and waited. TSMC, a rival Taiwanese foundry, put EUV into volume production in 2019; Intel's first EUV chips did not ship until 2023, a four-year gap in experience with the machines (05:41).

Out of that setback came a discipline Auth calls phase gating: a new material or transistor design has to hit defined yield, defect, and performance thresholds before it can graduate from early research into a product-bound "development" track (06:00). It is also why Auth insists on limiting how much new technology goes into any single node. Too much innovation at once, he says, makes the schedule unpredictable, and the schedule is what the customer is actually paying for.

A Transistor Learns to Wrap Around Itself

The spine of this whole story is a sixty-five-year-old idea: a transistor is a switch, and a gate sitting on top of a channel of silicon turns it on or off. As transistors shrank, the two ends of the switch, called the source and the drain, got close enough that current started leaking through even when the switch was supposed to be off. The fix each time has been to let the gate grip the channel from more sides. The planar transistor only touched the channel from the top. FinFET, first demonstrated in a lab in 1989 and put into Intel volume production in 2011, squeezes the channel into a vertical fin so the gate wraps it on three sides. Gate-all-around, demonstrated a year earlier in 1988 but not produced by Samsung until 2022, slices the channel into thin ribbons and wraps the gate completely around each one (09:07). Auth describes the shift in approach this way:

"The playbook's open. You can do all sorts of things out there... before, it was try to not change anything, to now it's like take the sledgehammer and start just tearing the thing up." — Chris Auth [12:54]

That sledgehammer era is why 14A pairs Gate-all-around with two more tricks: High-NA EUV and backside power. Numerical aperture, or NA, measures how wide a cone of light a lithography machine's mirrors can focus onto a wafer; a wider cone carves a finer line. Standard EUV machines run at an NA of .33. High-NA widens that to .55, letting a single pass print features about 1.7 times smaller (13:13). The catch is that High-NA machines cost roughly twice as much as standard ones, about $200 million versus $400 million, so they only pay off if they cut down on the extra printing passes that tight patterns otherwise require (14:06). Intel can use a single High-NA pass because it has also moved its power wiring to the back of the wafer, a change called backside power, which frees up space on the front side so signal wires are not packed as tightly (14:54). TSMC, which has not adopted backside power, still needs multiple EUV passes for its tightest patterns, so for TSMC, in Auth's words, High-NA "is not very helpful" yet (15:04).

Judgment Without a Complete Data Set

None of this happens on a clean, linear schedule. Kevin Fisher runs the meetings, called Hot Topics, where Intel decides which yield problems on its most advanced node get extra engineering attention and factory priority. He described a recurring failure mode called an epi nodule, a tumor-like defect that forms during epitaxy, the process of growing a crystal layer of material on top of the wafer (25:51). Diagnosing and fixing a nodule means running experiments in parallel without ever having a full picture of the cause, because, as Fisher put it:

"If you want to wait for a complete data set, you've waited too long. It's already too late." — Kevin Fisher [25:08]

So Fisher's actual job, he says, is deciding how much risk to accept on any given call, because every day lost is revenue lost. The riskiest experiments get routed through what Intel calls a hot box, a fast lane through the factory that jumps the queue at every tool, the chip equivalent of a highway carpool lane that slows everyone else down to speed one experiment through (29:00).

Further out, in Intel's research lab, the next generation of problems looks less like scheduling and more like chemistry. Copper, the metal used for on-chip wiring for decades, is losing ground at the finest dimensions because it requires a resistive "liner" layer to make it stick during deposition. Ruthenium does not need that liner, so below roughly a 20-nanometer wire pitch, it starts to beat copper on resistance (30:04). And the industry is edging toward CFET, a design that stacks a chip's two transistor types directly on top of each other instead of side by side, in principle doubling transistor density in the same footprint (21:48). The obstacle is not the stacking itself but what happens after: heat has nowhere clean to escape, and logic circuits generate far more of it than memory does, which is why 3D memory stacks like HBM are already common while 3D logic is not (22:22).

Packaging, the step that connects finished chips to each other, is further along. Hybrid bonding fuses the copper connections of two chips directly together, skipping the bulky solder bumps of older methods. Intel's current high-volume packaging, called Foveros, runs at a 25-micrometer pitch; its newer hybrid bonding reaches sub-10 micrometers, and a paper at this year's IEEE ECTC packaging conference reported working devices at a 0.45-micron pitch, another order of magnitude finer (45:29).

All of this physics runs into one hard limiter: tools. ASML, the Dutch company that makes essentially all EUV lithography machines, produces fewer than 100 of them a year and has no plans to significantly exceed that by the end of the decade (48:21). Every foundry and memory maker on earth draws from that same queue. Intel's CTO, Pushkar Ronde, notes that moving from the 18A process to 14A lets Intel reuse about 80% of its existing tool set (49:48), which matters because a fab's cost structure is roughly 80% fixed, so every extra point of utilization falls almost straight to revenue (53:36). Even with the reuse, scale still separates the two leading foundries: TSMC is spending roughly $50 billion a year on capital equipment against Intel's roughly $20 billion (58:36), and Ronde argues that the supply crunch is currently worse for memory chips than for logic compute (60:12). Lead times for top-end tools run about 18 months, which is why Ronde says production could beat forecasts in the near term but is unlikely to be meaningfully higher than expected by 2030 unless the whole supply chain, tool makers and their sub-suppliers included, ramps up together (60:32).

A single High-NA EUV scanner and its supporting equipment now cost about $400 million (63:31), a price that has roughly doubled every four to five years for decades. Project that line forward and the numbers stop making sense, which is part of why Ronde floats a more radical question: whether an industry that has spent thirty years protecting predictable schedules is due for a reset. "Sometimes it's good to sort of just start with a clean slate and rethink everything," he says, pointing out that today's clean-room orthodoxies, like yesterday's planar transistor, may simply be what engineers were taught rather than what the physics actually requires (66:41). Even Elon Musk's push to build an independent chip plant, nicknamed TeraFab, reflects the same constraint: Dwarkesh Patel observes that the bottleneck is not fabs but the tools that fill them, so a new factory does not add silicon to the world so much as it buys its owner a guaranteed place in the queue, to which Ronde replies "Mm-hmm" and adds that water, power, and consumables are also factors (61:46).